Development of Low-Power VLSI Architectures for Edge Computing Devices

Abstract

The rapid expansion of Internet of Things (IoT) and edge computing applications has increased the demand for energy-efficient hardware capable of performing complex computations with minimal power consumption. Conventional high-performance VLSI architectures often fail to meet the stringent energy constraints of edge devices, leading to reduced battery life and limited deployment in resource-constrained environments. This study focuses on the development of low-power VLSI architectures for edge computing devices, aiming to optimize power efficiency while maintaining computational performance. The methodology involves the design and analysis of power-efficient digital circuits using advanced VLSI design techniques such as voltage scaling, clock gating, power gating, and transistor sizing optimization. Architectural-level optimizations are also implemented to reduce switching activity and minimize dynamic and static power consumption. Simulation and synthesis of the proposed architectures are carried out using standard EDA tools to evaluate performance metrics including power dissipation, delay, area utilization, and energy efficiency. The results indicate that the proposed low-power VLSI designs significantly reduce overall power consumption compared to conventional architectures without compromising processing speed. Clock gating and voltage scaling techniques contribute substantially to dynamic power reduction, while power gating effectively minimizes leakage currents during idle states. It is also observed that optimized design trade-offs between speed and power enable efficient real-time processing for edge AI applications.